The present invention generally relates to solder bumping methods and structures. More particularly, this invention relates to a solder bumping method for a surface-mount (SM) device, which includes plating a solder material on a plating seed layer covering an under bump metallurgy (UBM), wherein the seed layer covers a much larger area than the UBM to increase the amount of solder material available to subsequently coalesce during reflow to form the solder bump on the UBM.
Surface-mount (SM) semiconductor devices such as flip chips typically include an integrated circuit and bead-like terminals formed on one of their surfaces. The terminals are typically in the form of solder bumps near the edges of the chip, and serve to both secure the chip to a circuit board and electrically interconnect the flip chip circuitry to a conductor pattern on the circuit board. The circuit board may be a ceramic substrate, printed wiring board, flexible circuit or silicon substrate, though other substrates are possible. Due to the numerous functions typically performed by the microcircuitry of a semiconductor device, a relatively large number of solder bumps are required. The size of a typical flip chip is generally on the order of a few millimeters per side, resulting in the solder bumps being crowded along the edges of the chip.
Because of the narrow spacing required for the solder bumps and their conductors, soldering a flip chip or other SM semiconductor device to a conductor pattern requires a significant degree of precision. Reflow solder techniques are widely employed for this purpose, and entail precisely depositing a controlled quantity of solder on the bond pads of the chip using methods such as electrodeposition and printing. Once deposited, heating the solder above its liquidus temperature serves to form the characteristic spherical-shaped solder bumps on the pads. After cooling to solidify the solder bumps, the chip is soldered to the conductor pattern by registering the solder bumps with their respective conductors and then reheating, or reflowing, the solder so as to form solder bump connections that metallurgically adhere to the conductors.
Flip chip input/output pads are electrically interconnected with the circuitry on the flip chip through vias. Because aluminum metallization is typically used in the fabrication of integrated circuits, input/output pads are typically aluminum or aluminum alloy, which are generally unsolderable and susceptible to corrosion if left exposed. In applications where copper metallization is used, copper pads are susceptible to being dissolved into the solder connections during reflow. Consequently, bond pads are often formed to include the input/output pad and one or more additional metal layers that promote wetting and metallurgical bonding with solder bump alloys. These additional metal layers, or under bump metallurgy (UBM), may be, for example, electroless nickel and a top layer of gold that will readily wet and bond with typical tin-lead solder alloys. Another suitable UBM composition has a multilayer structure that includes an adhesion-promoting layer, a diffusion barrier layer, and a solderable layer. The adhesion layer may be aluminum or another metal composition that will bond to the underlying aluminum input/output pad. Copper is readily solderable, i.e., can be wetted by and will metallurgically bond with solder alloys of the type used for solder bumps. Therefore, a thin layer of copper is a common choice for the top layer of the UBM. The diffusion barrier layer is typically a nickel-vanadium or chromium-copper alloy, and is disposed between the adhesion and solderable layers to inhibit diffusion between the solder and aluminum pad. A NiV and CrCu layer also serves as a wettable layer if an overlaying copper layer is dissolved into the solder.
Placement of the chip and reflow of the solder must be precisely controlled not only to coincide with the spacing of the bond pads and the conductors to which the solder bumps are registered and reflow soldered, but also to control the height of the solder bump connections after reflow. As is well known in the art, controlling the height of solder bump connections after reflow is often necessary to prevent the surface tension of the molten solder from drawing the flip chip excessively close to the substrate during the reflow operation. Sufficient spacing between the chip and its substrate, often termed the xe2x80x9cstand-off height,xe2x80x9d is desirable for enabling stress relief during thermal cycles, allowing penetration of cleaning solutions for removing undesirable processing residues, and enabling the penetration of mechanical bonding and encapsulation materials between the chip and its substrate.
Control of solder bump position, height and pitch are dictated in part by the manner in which the solder is deposited on the bond pads. One known technique is to use a photoimagable dry film as a stencil for printing a solder paste on the bond pads of a flip chip. The location and size of the solder bumps are determined by the vias in the dry film, which contain the solder during reflow. With relatively large bump spacings and conventional solders, this process is reliable and cost effective. However, for relatively fine pitches (e.g., a pitch of 200 micrometers or less), vias can be difficult to form in a dry film, and it is difficult to get a uniform distribution of solder paste into a small via. Finally, solder compositions that can be used with this method are limited to those with reflow temperatures at or below the maximum temperature the dry film material can withstand and still be removed after reflow.
Finer solder bump pitches can generally be obtained with plating methods. One such technique involves depositing metal films on the semiconductor wafer, forming a plating mask, electroplating a minibump of a solderable material, electroplating a layer of solder, and then removing the mask and the exposed metal films. The minibump and that portion of the metal film remaining beneath the solder serve as a UBM. A disadvantage to this approach is that chemistries used to remove the metal film between solder bumps must be compatible with and not degrade the bumps. Another disadvantage with solder plating is that the volume of solder that can be plated for individual bumps is limited. One technique to overcome this limitation is to pattern the plating resist with vias the size of the UBM, and then allow the solder to plate over the top of the resist and take on a mushroom-like shape. During the plating process, the solder above the resist plates laterally almost as fast as the solder plates vertically over the via. When the bumps are very closely spaced, the lateral growth of the mushroom shape must be limited to prevent neighboring bumps from growing together. An alternative technique used for fine pitch bumps is to use a very thick plating resist, resulting in a slow and expensive plating process. The control of solder volume is better when the plated metal is kept below the upper surface of the resist (i.e., entirely within the via) and the side walls of the bumps are defined by the resist rather than allowing the volume to depend on surface irregularities that inherently occur when the solder is plated to have a mushroom shape.
From the above it can be seen that, while fine solder bump pitches can be attained by plating techniques, process and material compatibilities between UBM formation, solder bump formation and reliability are limitations. Accordingly, it would be desirable if an improved method were available for forming fine-pitch solder bumps on flip chips and other SM semiconductor devices that employ solder bumps.
According to this invention, a solder bumping method and structure are provided that achieve fine solder bump pitches and eliminates conventional process compatibility requirements for UBM and solder bump formation. The method generally makes use of a semiconductor device having an input/output pad whose surface is provided with a solderable metal layer that serves as the UBM of the solder bump. A sacrificial layer is formed on the surface of the device to surround the metal layer. A plating seed layer is then formed on the metal layer and the surrounding surface of the sacrificial layer, after which a mask is formed on the seed layer and a via is defined in the mask to expose portions of the seed layer overlying the metal layer and the sacrificial layer. A solder material is then deposited on the seed layer exposed within the via.
Once the above structure is completed, the mask can be removed, followed by removal of a portion of the seed layer that is not covered by the solder material, leaving intact that portion of the seed layer beneath the solder material. The sacrificial layer is then removed, including that portion of the sacrificial layer underlying the seed layer, such that a gap is formed between the substrate and the remaining seed layer. Finally, the solder material is reflowed to form a solder bump into which the remaining seed layer is dissolved.
Because the via formed in the mask is not limited by the size of the metal layer, a considerably greater amount of solder material can be deposited than otherwise permitted if limited to the surface area of the metal layer. As a result, larger solder bumps that provide greater chip stand-off height are made possible with this invention. An additional advantage of the invention is that the via is not limited to the shape of the metal layer. In other words, while the metal layer may have a conventional circular shape, the via may have an oblong shape to further increase the amount of solder material available to form the solder bump. To achieve this latter advantage of the invention, the sacrificial layer serves an important role by preventing the seed layer and solder material from contacting portions of the device surface that are so remote from the metal layer as to lie outside of the perimeter of the resulting solder bump. The concern here is that the seed layer and solder material tend to leave metallic-based fragments on the surface of the device following solder bump reflow, and that these fragments might be detrimental to device performance. By separating the seed layer and solder material from the surface of the device that will be outside the perimeter of the solder bump, the likelihood is eliminated for the seed layer and solder material to leave metallic-based fragments following solder bump reflow that might cause electrical problems for the device.
From the above, it can be seen that the solder bump structure and process of this invention also enable the use of a solderable metal layer (UBM) that can be specifically formulated to promote the reliability of the resulting solder connection formed by the solder bump, without concern for process compatibility with the solder bump. Due to the presence of the plating seed layer, the solderable metal layer does not dictate the manner in which the solder material is deposited or the amount of solder material deposited, and therefore does not dictate the size of the solder bump formed by the solder material. Instead, the plating seed layer enables the mask thickness and via size and shape to determine the amount of solder material that can be deposited. Finally, the sacrificial layer further promotes the size of the via that can be formed, and therefore the amount of solder material available for the solder bump, without leaving potentially detrimental metallic residues of the seed layer and solder between solder bumps.
Other objects and advantages of this invention will be better appreciated from the following detailed description.